? semiconductor components industries, llc, 2002 april, 2002 rev. 7 1 publication order number: mc10e131/d mc10e131, mc100e131 5vecl 4bit d flipflop the mc10e/100e131 is a quad master-slave d-type flip-flop with differential outputs. each flip-flop may be clocked separately by holding common clock (c c ) low and using the clock enable (ce ) inputs for clocking. common clocking is achieved by holding the ce inputs low and using c c to clock all four flip-flops. in this case, the ce inputs perform the function of controlling the common clock, to each flip-flop. individual asynchronous resets are provided (r). asynchronous set controls (s) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. data enters the master when both c c and ce are low, and transfers to the slave when either c c or ce (or both) go high. the 100 series contains temperature compensation. ? 1100 mhz min. toggle frequency ? differential outputs ? individual and common clocks ? individual resets (asynchronous) ? paired sets (asynchronous) ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? metastability time constant is 200 ps. ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? esd protection: > 2 kv hbm, > 200 v mm ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 240 devices device package shipping ordering information mc10e131fn plcc28 37 units/rail mc10e131fnr2 plcc28 500 units/reel mc100e131fn plcc28 37 units/rail mc100e131fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e131fn awlyyww mc100e131fn awlyyww http://onsemi.com 128 128
mc10e131, mc100e131 http://onsemi.com 2 567891011 q 3 q 3 v cco r 2 ce 2 d 2 r 3 ce 3 d 3 s 12 v ee c c s 03 d 0 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 q 2 q 2 v cc q 1 q 1 q 0 q 0 ce 0 r 0 d 1 ce 1 r 1 nc v cco d 3 ce 3 r 3 d 2 ce 2 r 2 s 03 s 12 c c r 1 ce 1 d 1 r 0 ce 0 d 0 q 3 q 3 q 2 q 2 q 1 q 1 q 0 q 0 s d q q r s d q q r r d q q s r d q q s 1 pinout: 28-lead plcc (top view) * all v cc and v cco pins are tied together on the die. figure 1. pinout diagram warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. figure 2. logic diagram pin description pin function d 0 d 3 ecl data inputs ce 0 ce 3 ecl clock enables (individual) r 0 r 3 ecl resets c c ecl common clock s 03 , s 12 ecl sets (paired) q 0 q 3 , q 0 q 3 ecl differential outputs v cc , v cco positive supply v ee negative supply nc no connect
mc10e131, mc100e131 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junctiontocase) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 2) 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit i ee power supply current 58 70 58 70 58 70 58 70 ma v oh output high voltage (note 3) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 3) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv i ih input high current c c s r, ce d 350 450 300 150 350 450 300 150 350 450 300 150 350 450 300 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 3. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 4) 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit i ee power supply current 58 70 58 70 58 70 58 70 ma v oh output high voltage (note 5) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 5) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv i ih input high current c c s r, ce d 350 450 300 150 350 450 300 150 350 450 300 150 350 450 300 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 5. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e131, mc100e131 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 6) 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit i ee power supply current 58 70 58 70 58 70 67 81 ma v oh output high voltage (note 7) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 7) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv i ih input high current c c s r, ce d 350 450 300 150 350 450 300 150 350 450 300 150 350 450 300 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 7. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 8) 40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit i ee power supply current 58 70 58 70 58 70 67 81 ma v oh output high voltage (note 9) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 9) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv i ih input high current c c s r, ce d 350 450 300 150 350 450 300 150 350 450 300 150 350 450 300 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 8. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 9. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e131, mc100e131 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 8) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd mhz t plh t phl propagation delay to output ce c c r s 310 275 300 300 600 600 625 550 750 725 775 775 360 325 350 350 500 500 550 550 700 675 725 725 360 325 350 350 500 500 550 550 700 675 725 725 ps t s setup time (note 11) d 200 20 150 20 150 20 ps t h hold time (note 11) d 225 20 175 20 175 20 ps t rr reset recovery time 450 150 400 150 400 150 ps t pw minimum pulse width clk r, s 400 400 400 400 400 400 ps t skew within-device skew (note 12) 60 60 60 ps t jitter cycletocycle jitter tbd tbd tbd ps t r /t f rise/fall time (2080%) 275 460 725 300 480 300 480 675 ps 10. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. 11. setup/hold times guaranteed for both c c and ce . 12. within-device skew is defined as identical transitions on similar paths through a device. v tt = v cc 2.0 v figure 3. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d
mc10e131, mc100e131 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e131, mc100e131 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc10e131, mc100e131 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e131/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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